RISC-V is not a brand and not a chip. It is an instruction set: the contract that fixes which commands a processor understands, how many registers it has to work with and how it behaves in memory. It started in 2010 at the University of California, Berkeley as teaching material, and today it runs disk controllers, car switches, microcontrollers that cost pennies and the occasional Linux laptop. The odd part is not the electronics but the licence: anyone can implement that architecture without paying royalties or asking permission.
What exactly is signed when an ISA is signed
An ISA (instruction set architecture) defines three things at once: the repertoire of instructions the processor executes, the registers where it keeps working data, and the memory and privilege model through which it talks to the operating system. Everything above it —compiler, kernel, application— is written against that boundary. Everything below it —caches, execution pipeline, the whole microarchitecture— can change without breaking anything above.
That is why an ISA is a long-lived contract. x86 has honoured it since 1978 and still runs programs compiled three decades ago. The difference with RISC-V is who writes the document and who charges for it: in x86 two companies decide its future; in ARM one company licenses the design and charges for every part manufactured. In RISC-V the specification is public and distributed under permissive licences, so a factory can design its own core, change whatever it needs and sell it.
A minimal trunk and a set of letters
The design is modular, and that explains its name. RV32I, the 32-bit base, is barely forty instructions: additions, jumps, loads and not much else. From there everything is optional and named with letters: M adds multiplication and division, A the atomic operations that operating system locks need, F and D single and double precision floating point, C compressed 16-bit instructions to save space, V vectors and H hypervisor mode.
So the tag RV64GC summarises a whole processor: 64 bits, the general bundle of extensions (M, A, F, D) and compression. Hardware designers implement only what they will use; software developers compile for that specific combination. The price of so much freedom is obvious: if every vendor adds and removes pieces, a binary built for one may not boot on another.
Profiles, or how to tame the fragmentation
The answer to that problem is profiles: closed lists of mandatory and optional extensions for a given kind of product. The RVA23 profile, ratified in October 2024 for 64-bit application processors, makes the hypervisor and above all the vectors ratified in 2021 mandatory. The idea is that an operating system and a compiler can take that minimum for granted and ship binaries that work on any implementation meeting the profile. It is the same mechanism ARM used to tidy up its ecosystem, and what any distribution needs to package software once.
Vectors without a fixed width
The V extension deserves a paragraph because it changes the way you program. It does not fix the size of the vector register: it defines a VLEN that the hardware declares, and the software asks how many elements fit and then chains as many passes as needed. The same binary runs on a modest 128-bit core and on a 1,024-bit one without recompiling, which is not true of fixed-width vector instructions tied to one specific machine. For compute-heavy work —multiplying matrices, filtering signals, moving tensors of a neural network— that scalable model is exactly what people are after.
Where it stands today
The trail is more spread out than its fame suggests. Espressif’s ESP32-C3 and C6, present in thousands of consumer products, carry a RISC-V core; so do the controllers that manage hard drives and solid-state storage, where a small, cheap-to-manufacture core is what matters, and much of automotive electronics, because nobody wants to be tied to a single supplier across a car’s fifteen-year life. At the other end there are boards with eight out-of-order cores, accelerators for artificial intelligence and the occasional attempt at a laptop.
The software has followed the same path. The Linux kernel has kept a RISC-V port since version 4.15, in 2017; GCC and LLVM compile for it out of the box, Rust treats it as a first-class target and Debian and Ubuntu publish riscv64 images. Without that software, the architecture would have stayed an academic toy.
What is still missing
The obstacles are not about licences but about engineering and ecosystem. There is no high-end core yet that competes on performance per watt with the proprietary architectures; nor is there a market of recompiled commercial software that ships only as a proprietary x86 or ARM binary. Verifying that a design complies with the specification costs money, and RISC-V’s weak memory model forces programmers to be explicit about synchronisation barriers, something many have not had to think about for years. And every vendor can add its own extensions that do nothing for anybody else.
Even so, the game has changed in nature. For decades, choosing a processor meant choosing a supplier. RISC-V separates the two for the first time: the instruction contract becomes a commons, and competition moves to design, manufacturing process and price. For those who buy technology, and for those who fear being shut out by a licence, that is the important part.
