AMD has officially presented its new generation of data center processors, the EPYC “Venice” based on the Zen 6 architecture, at the Advancing AI 2026 event held in San Francisco. And it did so in style: it is the first x86 chip for servers manufactured on TSMC’s 2nm process, with Gate-All-Around (GAA), and offers up to 256 cores and 512 threads per socket. The company promises a 70% performance leap over the previous generation, the EPYC Turin (Zen 5), in a move that points directly at the heart of the artificial intelligence market dominated by NVIDIA.
What exactly is the EPYC Venice?
The EPYC Venice is AMD’s sixth generation of EPYC processors, and represents a deep redesign of the architecture. Where the EPYC Turin (Zen 5) used 16 CCDs (Core Complex Dies) around a single I/O Die, Venice halves the number of CCDs but more than doubles the cores per chip. The result: 8 CCDs with 32 Zen 6C cores each, flanked by two elongated I/O Dies instead of a central one.
The change to a dual I/O Die design is not cosmetic. By distributing the input/output load between two chips, AMD eliminates the bottleneck that previous generations suffered in memory and PCIe routing. The new SP7 socket supports 16 memory channels (compared to the 12 of Turin’s SP5), which translates into a bandwidth of 1.6 TB/s per socket, more than double the 614 GB/s of the previous generation.
TSMC N2: the first x86 on 2nm with Gate-All-Around transistors
If there is one fact that defines the EPYC Venice, it is that it is the first high-performance (HPC) processor to reach volume production on TSMC’s N2 node, the first of the Taiwanese foundry to use Gate-All-Around (GAA) nanosheet transistors. To understand why this matters: in traditional FinFET transistors, the silicon channel protrudes like a vertical fin crossed by the gate. In GAA, the gate wraps 360 degrees around horizontally stacked silicon sheets, offering far superior electrostatic control.
The practical advantages are compelling: 10-15% more performance at the same consumption, or 25-30% less consumption at the same performance, compared to the N3E node used in Turin. The transistor density exceeds 310 million per mm², versus the ~292 million of N3E. Each Venice CCD, of approximately 165mm² of N2 silicon, incorporates about 128 MB of L3 cache (following AMD’s 4 MB per core allocation), giving a potential total of 1,024 MB of L3 across the whole socket — the largest cache in an x86 server processor.
256 cores that change the game
AMD’s comparative table is clear: while the EPYC Turin (Zen 5) offered up to 128 cores in its standard configuration and 192 in the dense variant (Zen 5C), Venice raises the stakes with 96 standard Zen 6 cores and up to 256 Zen 6C cores. This represents a 33% increase over Turin’s maximum of 192 cores.
But performance does not grow only because of the cores. AMD claims that the new Zen 6 microarchitecture brings improvements in the front-end, branch prediction, and the memory subsystem that, combined with the new manufacturing node and the increase in bandwidth, produce that 70% generational improvement that the company has announced. That said, AMD has not specified which concrete workloads that figure is based on; we will have to wait for independent benchmarks to verify it.
PCIe 6.0 and the challenge to NVIDIA in AI
One of Venice’s most strategic moves is the adoption of PCIe Gen 6.0, doubling the bandwidth per lane to 128 GB/s per direction (versus the 64 GB/s of PCIe 5.0). With 128 or even 192 PCIe 6.0 lanes, Venice can feed the Instinct MI400X accelerators without becoming the bottleneck of the system.
AMD has been very explicit when comparing itself to NVIDIA: it claims that a complete Helios rack, which combines a 256-core Venice with 72 MI455X accelerators, exceeds by 3.3x the rack-level performance of NVIDIA’s Vera Rubin NVL72 system. That said, it is an internal AMD figure that has not yet been validated by independent third parties.
The Helios rack is AMD’s bet on the large-scale AI infrastructure market. Each rack contains 18 compute trays, each with four MI455X and one Venice. In total: 72 MI455X GPUs, more than 4,600 EPYC Venice cores, 31 TB of HBM4 memory (with 1.4 PB/s of aggregate bandwidth) and 2.9 exaflops of FP4 inference. The interconnect uses UALink over Ethernet, an open standard backed by AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft, competing directly with NVIDIA’s proprietary NVLink.
Competitive advantage over Intel
The launch of Venice comes at a particularly favorable time for AMD. The company already held a 46.2% share of server x86 CPU market revenue in the first quarter of 2026, according to Mercury Research — a record figure. Data center segment revenue reached 5.8 billion dollars, surpassing Intel for the first time in this segment.
And the competitive advantage is going to widen: Intel’s direct rival, the P-core Xeons (Diamond Rapids), will not arrive until 2027 according to Intel itself, manufactured on the Intel 18A-P node. That gives AMD at least a one-year advantage in the process node and in the high-performance data center CPU market.
It is not just a chip, it is a platform
It is worth noting that Venice is not compatible with the previous SP5 infrastructure. The new SP7 socket and 2.5D packaging force data centers to consider a complete server renewal, not a simple CPU upgrade. This can be an obstacle for some customers, but it is also a sign that AMD has chosen not to compromise the design to maintain backward compatibility.
In addition, the availability of the HBM4 needed for Helios’s MI455X is currently limited: all 2026 production is allocated to hyperscalers, and volumes for the general market will not arrive until 2027 according to independent analyses. This means that, although Venice as a CPU is already available, the full deployment of the Helios platform may take months for most enterprise customers.
What does all this mean?
The EPYC Venice is, on paper, the most advanced server processor AMD has ever created. First x86 CPU on 2nm, first GAA transistors in an HPC chip, 256 cores, PCIe 6.0, 1.6 TB/s of memory bandwidth, and a complete redesign of the chiplet architecture. The competition with NVIDIA is no longer only in GPUs: AMD is building a complete data center ecosystem where the CPU once again has a central role in the AI era.
The questions that remain open are the usual ones: how will these figures translate into real benchmarks? Will AMD’s ROCm software close the gap with CUDA? Will HBM4 volumes arrive in time to meet demand? We will start to see the answers in the coming months, but one thing is clear: the battle for AI infrastructure has a very serious new contender.
