You switch the computer off and its RAM forgets everything: that is the well-known part. What is told less often is that, even while the machine is running, that memory is “forgetting” non-stop and someone rescues it just in time, millions of times per second in every single cell.
A bit is a drop in a leaking bucket
Dynamic memory, the one that gives its name to DRAM (Dynamic Random Access Memory), stores each bit in a cell made of one transistor and one capacitor, the famous 1T1C structure. The capacitor is a tiny reservoir of electric charge: charged it represents a 1, discharged a 0. A single transistor acts as a gate to read or write the value.
The physical problem is unavoidable: charge escapes. No matter how well insulated the capacitor dielectric is, there is always a minimal leakage current, made worse by the transistor itself at rest. It is like a bucket with tiny leaks: you fill it and it slowly empties. The time a cell holds its data is called the retention time and, under normal conditions, it ranges around tens of milliseconds. Heat makes it worse: the hotter it runs, the more leakage and the shorter the retention time.
The fix was not to seal the bucket, but to refill it
Designing a perfectly sealed capacitor is extremely expensive and would break the density that makes DRAM cheap. Engineers chose the opposite path: accept the leak and refill the bucket before it empties. That periodic recharge is called refresh.
Memory cannot tell the operation apart from “write this 1 again”, so the memory controller reads the whole row and rewrites the same value before the charge drops below the threshold that the sense amplifier still recognises as a 1.
How often does it recharge?
The JEDEC standard, which defines DRAM specifications, sets a full-memory refresh every 64 milliseconds at normal temperature (in practice, each row is refreshed roughly every 8.8 microseconds). It is a constant cycle: your PC’s DRAM, even when “idle”, is busy with a silent, perpetual recharge.
When temperature rises, the controller speeds up and drops it to around 32 ms (the temperature-dependent refresh modes). In DDR5 the management is finer, with automatic modes and “all-bank refresh” that spread out when each bank recharges so data access is disturbed less.
The hidden cost: refreshing steals read time
Refreshing is not free. While a row is being recharged, nobody can read or write it, so refresh “steals” cycles from the controller. That is why DRAM carries a small performance overhead of roughly 2-5%, and why there is a low-power mode called self-refresh: when the system suspends, the chip itself takes over the recharge without the external controller, which lets the interface clock be switched off and saves energy.
When refresh fails: the row hammer
The refresh mechanics hides a notorious weakness. If an attacker opens (activates) the same memory row billions of times in a short window, that electrical bombardment makes neighbouring rows leak charge faster than expected and their bits flip without permission: the so-called row hammer. It is a real memory-integrity attack, used to escalate privileges on vulnerable systems.
The industry responds with mechanisms such as TRR (Target Row Refresh), which monitors which rows are activated with suspicious frequency and proactively refreshes their neighbours, and with the precision refresh management that DDR5 introduces.
Why another kind of memory is not used
There is an alternative, SRAM (Static RAM), which needs no refresh because it stores the bit in a six-transistor latch (6T) that keeps its state as long as there is power. But six transistors per bit make it huge and expensive: that is why SRAM is reserved for caches, where extreme speed and small capacity are needed, while DRAM, compact and cheap, dominates main memory.
So every time your computer seems to be doing nothing, it is silently holding billions of half-emptied buckets. Memory does not remember: it reminiscences.
